Integer Unit
Calculation of integres provide a parallel execution of assembly instructions into two bands integer seven levels (Fig. 4). Each of the two bands of assembly (X and Y) can process several instructions simultaneously.
Bands оntregi assembly containing the following levels of processing:-bringing the code instruction (Instruction Fetch-IF), instruction decoder-first (Instruction Decode 1 – ID1), the second instruction decoder (Instruction Decode 2 – ID2)-first address calculation block (Address Calculation 1 – AC1), the second calculation block address (Address Calculation 2 – AC2), execution (Execute – EX)-writeback (WB) (Fig. 4).
Fetching the instruction code level (IF) is shared by two bands of assembly, each 16 bytes of code make the drive cache in one clock cycle. In this level go to find any instruction that could occur in the flow of code and can affect normal program sequencing. If detected an unconditional jump instruction or a jump condition, predicting the leaps of logic that generates at a possible destination address for the jump instruction. Then bring RU code instructions from that address.
Instruction code decoding function is performed by ID1 and ID2 levels. ID1 level, used by both bands assembled evaluate code string of bytes sent by the FBI, and determine the number of bytes for each instruction. This level may submit up to two instructions in one clock pulse ID2 level, one for each pipelined.
The two levels ID2 decodes instructions and sends them to one of the two bands joining X or Y to execute. Pipelined 
instruction is chosen based on the type already in each band and how quickly it is assumed that they would finish.
Address calculating function is performed throughout the two levels: AC1, and AC2. If the instruction is a reference to an operand in memory, AC1 calculates a linear memory address instruction.
AC2 level performs all functions required for memory management, cache accesses and accesses to set records. If AC2 detects an instruction in floating point, it is sent to processing unit FPU.
Right in the execution (EX), it executes the instructions using operands received from the AC2.
Level writeback (WB) is the final work unit оntregi numbers. Right in that level or execution results are stored in the registers or write buffer cache unit.
Processing right in inordinate
If an instruction is executed faster than the previous instruction from other pipelined instructions are completed in inordinate. All instructions are processed in order to EX level. While the EX levels and instructions can be executed WB inordinate.
If there is data dependency between two instructions, which requires a block to ensure proper implementation of the program. Thus, even if inordinate instructions are executed, writing the instructions and exceptions are always made in the order required by the program.
Selection band performance
In the majority of cases, the instructions are processed in either of the two bands of assembly and no constraints on the type of instructions executable in parallel in the two bands of assembly. However, some instructions can be processed only pipelined X:-jump instructions, floating point-instructions, directions, exclusive.
Instructions in floating jump and can be executed in parallel with another instruction can be executed in band Y Exclusive instructions may be executed in parallel with any instructions. These instructions require multiple memory accesses. Even if these instructions are executed exclusively used hardware from two lanes to expedite completion of assembly instruction. The following are types of instructions strung exclusive processor 6×86: Safe mode-loading segments, special-access to your records (control registers, debug and test), instructions on strings,-multiplying and dividing, accesses to ports I / Oh, and POPA, PUSH,-intersegment jumps, procedure calls and out of intersegment procedures.
Addressing the data dependencies
Cвnd two instructions are executed in parallel access the same day or the registry, may appear from the following types of data dependencies: if read-write (Read-After-Write – RAW) as read-write (Write-After-Read - WAR), write-after write (Write-After-Write – WAW).
Dependencies between data normally requires serialization implementation instructions involved. But 6×86 implements three mechanisms that allow parallel execution of instructions containing data dependencies between:-renaming registers (Register Renaming)-оnaintarea data (Data Forwarding), data-avoidance (Date bypassing). Right in below, will briefly describe these meacnisme.
Renaming registers
Cyrix 6×86 processor contains 32 general purpose physical registers. Each of the 32 books of the file registers can be designated as one of general purpose registers of the x86 architecture (EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP). For each write operation in a register is selected a new physical register, to temporarily retain the previous day. Renaming registers virtually eliminates all WAW and WAR dependencies. This mode is transparent to the programmer to rename registers, is transparent to both operating system and programs application.
Sample 1. Register renaming eliminates write after reading such dependencies (WAR). A WAR type dependence occurs when the first of a pair of logical register instructions read and write both the second instruction register. This dependency is illustrated by the pair of instructions below:
band X-band Y
(A) MOV BX, AX (2) ADD AX, CX
(BX <- AX) (AX <- AX + CX)
(Initial sequence of program instructions is shown by numbers in parentheses.)
Right in the absence of renaming registers in pipelined instruction ADD Y should wait until the pipelined instruction MOV X should read the AX register.
The processor avoids blocking 6×86 strip assembly in such a situation. As each instruction is executed, the results are placed into a new physical register to avoid the possibility of overwriting a value to a logical register and to allow parallel execution of two instructions without locking (without requiring any sequencing to accessing the same resource.
Example 2. Register renaming eliminates write dependencies such as write (WAW)
WAW dependency occurs when two consecutive instructions in writing out the same logical register. This dependency is illustrated by:
band X-band Y
(1) ADD AX, BX (2) MOV AX, [mem]
(AX <- AX + BX) (AX <- [mem])
No name records of pipelined instruction MOV Y should be discontinued to ensure that the X-band ADD instruction has submitted the result in AX.
