Due to the vast spread of DRAM type memory, I will exemplify the functioning of the memory cell based on this technology. A memory cell is the smallest unit of physical memory. It is composed of discrete electronic components. The operating principle is actually changing the logical state between 0 and 1, that is found at the physical level. Depending on the technology used, the memory corresponds to the storage of electrical energy through a capacitor (DRAM), or to the reconfiguration of the array of transistors (SRAM).
The memory cell is logically treated as a bit. The smallest unit of addressable logical memory is composed of eight bits. This combination offers the possibility of obtaining 256 characters. For constructive reasons related to design, the memory cells are organized in the form of matrices. To identify and access the memory cells, they have a unique address for each cell separately. Identifying the memory cell is done by sending the bus the address and the address decoder (consisting of line and column decoders), identifies the memory cell corresponding to its address and transmits the received data. Further, the data is transmitted back using the bus.
The bus is the connection between the motherboard chipset and memory, this is the bridge where the addresses are transmitted to the decoder. The address decoder comprises line and column decoders, it receives the address of the memory cell that divides into two parts, first part being sent to the line decoder and the second to the column decoder, thus identifying the corresponding memory cell.
The matrix structure in which are present the memory cells is arranged on rows and columns. This interface contains a signal amplifier, it receives information stored in the memory cells, amplifies the signal, recalls the memory and transmits the information through the data bus towards the chipset (if that information is read from memory). The writing process is reversed when the information comes from the processor to the memory.
The data bus is the connection between the motherboard chipset and the memory, it offers the possibility of transmitting information that must be processed by the processor or stored in the memory. In general, memory cells cannot be accessed individually, therefore, a constructive memory array is encapsulated in a chip. The memory chips are assembled on a memory module (PCB) in number of eight. They are connected to the bus and data bus. So you get a virtual memory cell, consisting of 8 bits (one byte). The memory modules, at their turn, are organized in memory banks, they are connected together in the same manner as chips.
If we take the example of a processor that works on a 16-bit SIMM memory module, that type works only in pairs. This is a rather old form of memory. This use of pairs happens because the CPU needs to fill 16-bit using the data bus, taking into account that a memory module has only 8 bits, so two such modules are connected together, in this way they will obtain a data bus width of 16 bits.
The waiting times for all the operations that bring data into the interface, need a while to do that, which is identified as the “latency”. So, for transmitting the addresses from the processor, chipset and memory, the computer uses two cycles. To identify the memory cell, it takes up to two operations. For line identification of the matrix, it needs 2 / 3 cycles (depending on the capacity of the used memory), this period is called RAS (Row Address Strobe) and CAS (Column Address Strobe) For identification of the column (CAS latency) it consumes about the same time as the first operation (2 / 3 cycles). To send information to a data interface, the time consumed is about another 2 cycles.
After transmitting the information, in case the process of emission has a width greater than the data bus, these data are transmitted to the processor in the “burst mode”. The “burst mode” for each clock cycle, is possible due to the large internal activity for finding the column and line.
The main advantage of the dynamic memory (DRAM) is its very small price. But the performances are still far behind the SRAM memory. Because of the way in which the switching between the states 0 and 1 and the way of reading, that a memory cell has, SRAM does not need to rewrite the data after they have been read and refresh the memory cell. The access times are much smaller and the speed at which this type of working memory reaches its performance far outweighs the dynamic memory. Due to the high cost price of a SRAM cell, this type of memory is used only for making the cache and is implemented in motherboards as level 2 cache (L2) or level 1 cache (L1), which is integrated in processors in the structure of the computer. L1 cache runs at the same frequency as the CPU L2 cache and the memory frequency is at the half of the processor frequency.
The cache was introduced as a technological trick that must fill the gap between the processor and memory frequency.
