Caches
I have written repeatedly about the PC Report caches (eg March 1997 and November 1998). Here we just throw them on the surface; our goal is to understand why the cache sites play a fundamental role in raising performance. Figure ‘performance – memory and CPU “gives us the key: while both processors and memory speed increases steadily, increasing processor is 50% faster than memories. As such there is a growing disparity between the needs of data (and instructions) of the processor and what memory can provide, during a memory access to reach tens of clock cycles for modern processors. Access delay is further exacerbated when systems have multiple processors, in which case data access time can reach thousands of cycles.
For this reason caches are constructed that are smaller and faster memory, which is placed between the processor and main memory, and are brought for processing data. Designers were able to increase the effectiveness cache sites using two methods:
(A) The use of caches ever larger, placed ever closer to the processor. This trend is clearly visible: 
The first processors did not have any cache memory that was fast enough to serve their data. In 1980 appeared caches (L1) in the form of special circuits, which in 1984 were integrated on the same pillow with central processor silicon, after which (1986) appeared a second level cache (L2), higher and somewhat slower, which in modern processors (1995) is in turn often integrated circuit microprocessor, to allow quick access.
(B) On the other management methods of the cache sites are becoming more sophisticated:
Occurred caches serving first word processor as soon as it arrived, even though the rest are coming (early restart, 1992) locks not caches CPU when data is missing, but allow it to continue execution (non-blocking, 1994) and all sorts of other sophisticated technologies, they have made elsewhere (victim caches, write buffers, special instructions (prefetching) cache management, etc.).. Here we should mention multiprocessors symmetric and of cache coherence protocols for sites such systems, all modern processors are designed for use in multi-processor systems, and include such devices.
Contemporary architectures
Thus, following the development architectures, we got up today. We will try to characterize briefly state architectures, and then we look at some of future directions.
Hardware and software: The modern history of two opposed paradigms for increasing processor performance based on software and hardware respectively. Apparently, an article about processor architecture has nothing to do with software. Nothing wrong: this time there is a total symbiosis between hardware and software. Designing processors with compiler they use and their relationship is very close: the compiler must generate code to exploit the architectural features; otherwise the generated code will be very ineffective.
Methods of increasing performance with static compilers are known because the program is analyzed and optimized once, before being started running. Hardware-based methods are called dynamic because they are applied while the program is running.
History Architecture always opposed the two paradigms: eg initial debate RISC / CISC was the same kind, as the debate between superscalar and VLIW, which I already mentioned in the text.
Note: In the ’80s came the idea to make processors much easier to allow them to go faster. Such architectures have been called RISC: Reduced Instruction Set Computer, by contrast with other, CSI Complex.
In fact, as noted in other articles (eg PC Report June 1999), there are things you can do only things that are static and may only be made dynamic. So actually, even architectures that start at one end, tend to converge by using a mixture of traits from both areas:
Currently we distinguish RISC / CISC almost faded. For example, Pentium, a typical CISC processor actually which automatically translate the instructions into RISC instructions in hardware, where it is performing. Moreover, all RISC processor instruction set extensions acquired (like CISC) to increase their effectiveness, for example, all processors have special multimedia extensions.
Also, the boundaries between super-scalar and VLIW tend to fade, each borrowed from other technologies.
Certainly a mixed model is preferable because it can get the best of each technology.
Crusoe
It is appropriate to note a resurgence of “fight” Pure systems: this year the company Transmeta has announced the arrival of a new processor called Crusoe, which operates in more than static technologies (compilation). Company Transmeta has made great surprise, not so much by their processor, which can simulate other processors, including Intel’s business, but that it engages the planet’s most famous programmer, Linus Torvalds, creator of Linux.
Transmeta Crusoe launched with great pomp in January, the company preaches a return to simplicity (which was suggested as current RISC and VLIW models), the hard drive is fast and simple and the compiler takes the brunt. The team that worked on Transmeta is largely composed of engineers leave from IBM: IBM has been working on a version of the PowerPC processor that can do exactly the same thing could run in native mode x86 code (ie Intel-compatible), but their project was discontinued when it was a very advanced state, apparently for marketing reasons.
How serious is this new competitor?
Unfortunately Crusoe’s strengths are not too clear:
• a clock chip is not faster than Intel processors (Crusoe versions available now only go to 400Mhz, compared to Pentium, which reached 800);
• chip indeed consume much less energy and needs much less cooling. Transmeta claims that this makes it ideal for laptops. Unfortunately, the main consumer of energy in a laptop is the processor, but the screen and disc, so the benefits of the new chip will be marginal;
• Crusoe enjoy compatibility with the x86 instruction set, but on x86 platforms is dominant (desktops, laptops, even a server) I saw that his performance is weak. If Crusoe wants to compete for other markets, embedded processors (embedded computing), it has to do with other formidable competitors as signal processors from Motorola, Texas Instruments and Intel (ARM), on which it is not clear how many has advantages.
Perhaps to remain viable, Crusoe will be metamorphosis and become more complicated, using a series of dynamic mechanisms to increase performance.
Ultimately there is one resource that is almost free and sufficient number of transistors. Thanks to miniaturization of transistors available design number increases enormously so simple at all costs (as a Crusoe embodies) is not necessarily quality.
